Use of Dual Mode Processors and Droop in Mobile Computer Applications
Modern notebook computers employ advanced processors with high clock rates that place higher demand on the battery life and impose higher thermal stresses on to the circuit components. To enable systems with higher performance without compromising battery life, dual mode processors were introduced. These processors operate on higher clock rates and higher voltage when the notebook is powered from the wall adapter (so-called xe2x80x9cperformance modexe2x80x9d). When battery power is used, the operating voltage and the clock frequency are simultaneously scaled down to reduce the consumed power without greatly compromising the computing performance. This is so-called xe2x80x9cbattery-optimized modexe2x80x9d. In battery-optimized mode consumed power is about 40% less than during performance mode with almost equal contribution from the frequency and the voltage scaling.
Power dissipated by a processor is proportional to the clock frequency and to the applied voltage squared.
PCPU=Kxc3x97FCPUxc3x97VCPU2xe2x80x83xe2x80x83(1)
Considering that the processor power is a product of the operation voltage and the current PCPU=VCPUxc3x97ICPU, the processor current is proportional to the processor operating frequency and the voltage applied.
ICPU=Kxc3x97FCPUxc3x97VCPUxe2x80x83xe2x80x83(2)
Many computer power management systems deliberately xe2x80x9cdroopxe2x80x9d the CPU voltage to control impedance of the DC/DC converters and to reduce the number of the capacitors required to handle the processor supply current transients. The output voltage of the converter with a droop is inversely proportional to the load current. Reduced power is a key benefit of using the DC/DC converter with a droop to power the processor in the notebooks or other mobile applications with power and thermal constrains. Because the processor power is proportional to the supply voltage squared, even small reductions in the output voltage within the tolerance window translate into measurable reductions in the power dissipated. The additional power reduction may be about 10% and results in extra battery life.
The FIG. 1 illustrates one known method of implementing droop in the DC/DC converter. The converter 10 includes a DC source VIN that is selectively coupled to a power switch 14. The switch 14 may include one or more power devices in the form of a bridge. The output current IO is connected to the load RL via an inductor 24 and a capacitor 26. The output current is sensed as current ICS and is connected to a current gain circuit 30. The output of the current gain circuit is the current IDROOP. It is coupled to a node 36 at one input of error amplifier 50. Also connected to the node 36 is resistor R1 and the RC feedback circuit of CCOMP and RCOMP. The other input to the error amplifier is provided by the digital to analog converter (DAC) 40 and buffer amplifier 42. They set the reference voltage for the error amplifier 50. The output of the error amplifier is connected to one input of a comparator 60. Its other input receives a ramp signal. The output of the comparator is connected to a latch 18 that is controlled by a clock signal CLK. The output of the latch 18 controls the operation of the power switch 14 to the turn the DC power on and off.
The sensed current signal ICS is proportional to the load current Io, ICS can be either inductor current, or switch current, or diode (or synchronous switch) current. It is scaled down and transformed into the current IDROOP that creates a feedback signal as the voltage drop across the resistor R1. At the input of the voltage-loop error amplifier IDROOP is summed with the voltage feedback signal. As a result, the output voltage of the converter 10 is lowered proportionally to the sum of the droop and load currents. In other words, by changing the fed back voltage from the load voltage to the load voltage less the desired droop, the output of the error amplifier and the power supply is adjusted to provide the desired droop.
The output voltage of the loaded converter varies in accordance with the following equation.
VCPU(I)=VCPU(0)xe2x88x92VDROOP(I),xe2x80x83xe2x80x83(3)
Where:
VCPU(0)=VDACxc3x97(1+xcex94/2)xe2x80x94is the output voltage with no load. This voltage is usually somewhat higher then nominal voltage commanded by the DAC reference. Normally, the droop is centered to the half-load current. It means that at half-load current the output voltage is equal to the voltage commanded by the DAC.
xcex94xe2x80x94is the desired droop value given as a fraction of the VDAC.
VDROOP(I)=R1xc3x97GCxc3x97ICPUxe2x80x94is the droop in the output voltage due to load currentxe2x80x94proportional voltage-drop across the resistor R1. The above droop circuit and other droop circuits are shown and described in U.S. patent application Ser. No. 09/591,560 filed Jun. 9, 2000, assigned to the owner of this invention and incorporated herein by reference.
When the dual mode processors are used, it is desired to have an adequate droop (equal fractions of the commanded output voltage) in both modes of operation. The known droop method does not provide relatively equal droop for the different operation modes because the gain in the current feedback loop is constant. Indeed, constant gain is a fundamental characteristic of conventional negative feedback circuit designs.
Using (2) and (3), the equation for the converter 10 output voltage can be obtained in the following form, which shows that the converter output voltage is not only inversely proportional to the load current but is also inversely proportional to the processor clock frequency FCPU max.                                                                                                               V                    CPU                                    ⁡                                      (                    I                    )                                                  =                                  xe2x80x83                                ⁢                                                                            V                      DAC                                        ⁡                                          (                                              1                        +                                                  Δ                          2                                                                    )                                                        -                                      R1                    xc3x97                                          G                      C                                        xc3x97                    K                    xc3x97                                          F                                              CPU                        ⁢                                                  xe2x80x83                                                ⁢                        max                                                              xc3x97                                                                                                                                            xe2x80x83                                ⁢                                                      K                    f                                    xc3x97                                                            V                      CPU                                        ⁡                                          (                      I                      )                                                                                                          ⁢                  
                ⁢                                            V              CPU                        ⁡                          (              I              )                                =                                                    V                DAC                            xc3x97                              (                                  1                  +                                      Δ                    2                                                  )                                                    1              +                              R1                xc3x97                                  G                  C                                xc3x97                K                xc3x97                                  F                                      CPU                    ⁢                                          xe2x80x83                                        ⁢                    max                                                  xc3x97                                  K                  f                                                                                        (        4        )            
Where:
FCPU maxxc3x97Kƒ represents variable processor performance, which varies due to modulating multiplier Kƒ=0 . . . 1. This multiplier simulates the factor how the processor is engaged by the software. When Kf=0, the processor idles and its current is close to zero. When Kf=1, the performance and the load current have their maximum values. This model is involved for illustrative purposes only to evaluate the considered solutions and does not cover all the aspects of the processor operation.
The value of the gain constant GC for circuit 30 of converter 10 can be found as:                               G          C                =                                            2              xc3x97              Δ                                                      (                                  2                  -                  Δ                                )                            xc3x97              R1              xc3x97              K              xc3x97                              F                                  CPU                  ⁢                                      xe2x80x83                                    ⁢                  max                                                              .                                    (        5        )            
The droop is usually tuned to handle the worst case transient that is associated with the performance mode where the processor current is high. When the processor is switched to operate in the battery mode, the operating frequency and voltage are scaled down. In this case, the processor current is significantly lower, the droop is much smaller and its benefits deteriorated. If gain was tuned to create the optimal droop for the battery-optimized mode, the droop becomes excessive in the performance mode.
The following examples illustrate this asymmetrical feature of droop versus processor mode. For example, a known dual mode processor has the following power parameters at high performance mode: V1=1.6 V, Imax=10.2 A, F=600 MHz, where V is the processor voltage, Imaxxe2x80x94is the maximum processor current, Fxe2x80x94is the clock frequency. In the battery mode these parameters are V2=1.35 V, Imax 6.8 A, F=500 MHz. The current feedback gain is set to achieve 5% droop. In the first case, the droop is tuned to the performance mode. In the second case, the droop is tuned to be optimal in the battery-optimized mode. In both cases the processor constant is equal to 10.5 nF.
The results in Table 1 show that it is impossible to tune the droop in the known converter to be satisfactory for both operation modes. For example, when droop is tuned for the performance mode, only 84% of the desired droop range is used in the battery-optimized mode.
FIG. 2 graphically illustrates how the converter voltage depends on the load current in different modes of operation. The Kf factor helps to do that using the same scale. It can be easily seen that in the performance mode (VCPU1) the droop is perfectly centered and its value complies with the design goal. The xc2x1xcex94% is xc2x12.5. Inversely, in the battery optimized mode (VCPU2) the output voltage reaches the nominal value at about 60% of the load and the droop range is not completely used. This can lead to the situation when the converter output voltage violates the load transient specifications at fast load change.
To provide an equal droop the converter output characteristic should have either a) different slope; e.g. current gain at different FCPU max to provide relatively equal droop in the performance and the battery optimized modes, or b) a different offset voltage applied to the error amplifier reference input depending on FCPU max, or c) a fixed droop regardless of operating conditions, or d) a combination of such features to provide for symmetrical droop.
The invention solves the problem of deteriorating or asymmetrical droop by adjusting the droop in accordance with the operating mode of the processor. In its broader aspects, the invention provides a novel method and apparatus for adjusting droop to match and compensate for changes in operating modes.
The method of the invention is used in an electronic system having a DC/DC converter that operates in one of at least two modes of operation for supplying power to a processor in the electronic system. Each mode of operation includes a nominal operating voltage, operating frequency and operating current. The steps of the method include comparing an output DC voltage to a reference DC signal that represents the desired DC output voltage, generating a pulse-width-modulated control signal, by comparing the error signal with a ramp signal, or by other means known in the art of DC/DC converters. The pulse width modulated signal is converted into the desired DC output voltage by usual circuit components, such as an inductor and a capacitor. The DC output voltage is applied to the load. The method uses one of several known circuits for generating droop voltage.
In the preferred embodiment, the voltage droop is adjusted with a feedback loop. In the feedback loop the method sums one signal dependent upon the output DC voltage with a first signal dependent upon the load current and a second signal dependent upon the operating mode. In response to a change in operating mode the feedback loop adjusts the voltage droop signal to be substantially symmetrical.
In one embodiment the invention alters the slope of the load line to adjust the voltage droop to provide relatively equal droop provided in each mode of operation. In a second embodiment the invention alters the slope of the load line to adjust the droop to provide a droop that is centered and has a constant absolute value in any of selected operating modes. In a third embodiment the invention offsets the reference of the feedback amplifier to adjust the droop to provide a relatively equal droop in each mode of operation without altering the slope of the load line.
The method of the invention is implemented in several novel embodiments. Each embodiment has customary elements including a power switch that includes a MOSFET bridge, a comparator and a latch. The comparator has one input supplied with a conventional ramp function. The other input is supplied by the variable gain feedback loop. That loop includes an error amplifier having first and second inputs and generates an output error signal for controlling droop of the output voltage of the converter. The first input is a summing input that is electrically connected to the output voltage and the output current of said DC/DC converter. The summing input is configured for adding together signals that depend upon the output voltage and the output current. The second input of the error amplifier receives a reference signal that depends upon the desired operating voltage of the processor. The error amplifier generates an output error signal and adjusts its error signal depending at least in part upon the output voltage and the output current. A means for adjusting the power supply droop about the median of the operating voltage of the processor is coupled to one of the input of the error amplifier and depend upon the mode of operation of the processor including the operating voltage, operating current or operating frequency. The comparator receives the error signal and the ramp signal and has its output connected through a latch to control the power switch/bridge. The power switch has an on condition and an off condition. The converter is configured for supplying dc current to the load when in said on condition. The power switch has a control input electrically connected to said comparator output signal. The power switch responds to the output signal of the comparator to change between its on and off conditions.
In one embodiment the adjusting means coupled to the input of the error amplifier is a circuit that receives (a) a signal inversely proportional to the operating frequency of the processor and (b) the output current signal. The adjusting means generates the first input signal to the error amplifier so that its first input signal depends upon the product of the (a) signal inversely proportional to the operating frequency of the processor and (b) the output current signal. This changes the slope of the load line of the converter upon the processor""s operating mode.
In another embodiment when reduction in the processor consumption in battery-optimized mode is anticipated to be achieved by approximately equal contributions of voltage and frequency scaling, the adjusting means is a multiplier circuit that includes a matrix current decoder. It includes a plurality of current sources of different currents. A first input corresponding to the output current is connected to all the current sources, a second input corresponding to the operating voltage of the processor selects a current source inversely proportional to the operating voltage and generates the first input to the error amplifier. That input changes the slope of the load line of the converter upon the processor""s operating mode.
In another embodiment when a constant processor operating mode independent droop is desired and reduction in the processor consumption in battery-optimized mode is anticipated to be achieved by approximately equal contributions of voltage and frequency scaling, the adjusting means coupled to the input of the error amplifier is a circuit that receives a (a) signal inversely proportional to the operating frequency of the processor, (b) a signal inversely proportional to the processor set voltage and (c) the output current signal. The adjusting means generates a first input signal to the error amplifier so that its first input signal depends upon the product of the (a) signal inversely proportional to the operating frequency of the processor, (b) signal inversely proportional to the processor set voltage and (c) the output current signal. This changes the slope of the load line of the converter upon the processor""s operating mode in the way that droop has a constant absolute value in any mode.
In another embodiment when a constant processor operating mode independent droop is desired, the adjusting means is a multiplier circuit that includes a matrix current decoder. It includes a plurality of current sources of different currents. A first input corresponding to the output current is connected to all the current sources, a second input corresponding to the operating voltage of the processor selects a current source inversely proportional to the operating voltage squared and generates a first input to the error amplifier. That input changes the slope of the load line of the converter upon the processor""s operating mode in the way that the absolute value of the droop remains essentially the same despite of changes in processor operating modes.
The DC/DC converter may alter the feedback loop by providing a voltage source to offset the second (reference) input of the error amplifier. In that case the DC/DC converter has a buffer amplifier with a variable gain. It receives a gain control signal that depends upon the processor operating voltage or upon the operating frequency of the processor. The buffer amplifier generates the second (reference) input to the error amplifier to offset the droop by both the processor frequency and the processor voltage. This offsets the droop upon processor operating mode without changing the slope of the converter output characteristic.
A further embodiment of the invention includes a buffer amplifier with a gain control signal generator that includes a matrix decoding circuit. It has a plurality of resistors with its transfer gain inversely proportional to the processor voltage. This offsets the droop upon processor operating mode and in high degree symmetrically positions it along the half-load current.